VLSI Desgin/Experts

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Jitendra

Available
  • Knowledgeability 7.50
  • Clarity of Response 8.00
  • Politeness 8.50
  • Response Time(hr) 22.5
  •  --Last 90 Days(hr) N/A
  • Total Questions 19
 VHDL, FPGA, Modelsim (Simulation tool), Digital Design Issues

Rajaraman N

Available
  • Knowledgeability N/A
  • Clarity of Response N/A
  • Politeness N/A
  • Response Time(hr) 16.9
  •  --Last 90 Days(hr) 5.3
  • Total Questions 4
 Question related to RTL design, Verification side, Verlig coding, Board design

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