VLSI Desgin/Experts

ExpertAverage RatingsExpertise

Rajaraman N

Available
  • Knowledgeability N/A
  • Clarity of Response N/A
  • Timeliness N/A
  • Politeness N/A
  • Total Questions 3
 Question related to RTL design, Verification side, Verlig coding, Board design

Jitendra

Available
  • Knowledgeability 7.50
  • Clarity of Response 8.00
  • Timeliness 9.00
  • Politeness 8.50
  • Total Questions 18
 VHDL, FPGA, Modelsim (Simulation tool), Digital Design Issues

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