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VHDL, FPGA, Modelsim (Simulation tool), Digital Design Issues
IP CORE developement for SONET.
Memory model developement.
Synthesis, Formal Verification, MBIST for ASIC design
| User | Date | K | C | P | Comments |
|---|---|---|---|---|---|
| pratik chopra | 06/22/05 | 7 | 8 | 9 | thanks for immediate response |
| safaa | 05/23/05 | 8 | 8 | 8 | thanks, |

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